1. Field
Example embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a technique for reducing a word line current in a semiconductor memory device using a variable resistor as a unit memory cell.
2. Description of the Related Art
The next-generation non-volatile memory devices without a refresh operation have been developed in order to increase memory capacity and reduce power consumption. In recent years, for example, the following next-generation memory devices have drawn attention: a phase change random access memory (PRAM) using a phase change material; a resistive random access memory (RRAM) using a material having variable resistance characteristics such as a transition metal oxide; and a magnetic random access memory (MRAM) using a ferromagnetic material. The materials forming the next-generation memory devices are common in that their resistance values vary depending on a current or a voltage and they do not require a refresh operation due to their non-volatile characteristics in which the resistance value is maintained after the supply of the current or voltage is cut off.
In the next-generation memory device, during a write operation, when a large amount of write current flowing through a plurality of memory cells flows to one word line, a word line voltage is increased. In addition, during a read operation, when a read current is supplied to one word line through a plurality of memory cells, a word line voltage is increased. As a result, a desired amount of write current or a desired amount of read current does not flow, which results in an error in the write or read operation.
Therefore, measures to prevent an increase in word line voltage during a data access operation are required.